june 2009 doc id 15894 rev 1 1/9 9 ESDA14V2-1BF3 single-line bidirect ional transil? array for esd protection features esd protection: iec61000-4-2 level 4 low leakage current very small pcb area < 0.4 mm2 400 micron pitch complies with the following standards iec61000-4-2 level 4 ? 15 kv (air discharge) ? 8 kv (contact discharge) applications where transient overvoltage protection of esd sensitive equipment is required, such as: computers printers communications systems and cellular phones video equipment description the ESDA14V2-1BF3 is a monolithic bidirectional diode designed to protect 1 line against esd transients. the device is ideally suit ed for applications where both reduced line capacitance and board space saving are required. figure 1. schematic diagram (top view) tm: transil is a trademar k of stmicroelectronics flip chip (2 bumps) www.st.com
characteristics ESDA14V2-1BF3 2/9 doc id 15894 rev 1 1 characteristics figure 2. electrical characteristics (definitions) table 1. absolute maximum ratings (t amb = 25 c) symbol parameter value unit v pp peak pulse voltage: iec61000-4-2 air discharge iec61000-4-2 contact discharge 15 8 kv p pp peak pulse power dissipation (8/20 s) (1) t j initial = t amb 50 w t j junction temperature 125 c t stg storage temperature range - 55 to +150 c t l maximum lead temperature for soldering during 10 s 260 c t op operating junction temperature range -40 to +125 c 1. for a surge greater than the maximum val ues, the diode will fail in short-circuit symbol parameter v rm stand-off voltage v br breakdown voltage v cl clamping voltage i rm leakage current @ v rm r d dynamic resistance t voltage - temperature coefficient c line line capacitance table 2. electrical characteristics (values, t amb = 25 c) symbol test condit ion min. typ. max unit v br i r = 1 ma 14.2 - 18.0 v i rm v rm = 12 v --0.5 a v rm = 3 v --0.1 r d square pulse, i pp = 3 a t p = 2.5 s - 2.2 - t v br = t(t amb - 25 c) x v br (25 c) - - 6.5 10 -4 /c c line v r = 0 v, f = 1 mhz, v osc = 30 mv - 10 - pf
ESDA14V2-1BF3 characteristics doc id 15894 rev 1 3/9 figure 3. relative variation of peak pulse power versus initial junction temperature figure 4. peak pulse power versus exponential pulse duration 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 25 50 75 100 125 150 p pp [t j initial] / p pp [t j initial=25c] t j (c) 1 10 100 1000 1 10 100 1000 p pp (w) t j initial = 25 c t p (s) figure 5. clamping voltage versus peak pulse current (square pulse, typical values) figure 6. junction capacitance versus reverse applied voltage (typical values) 0.1 1.0 10.0 15 16 17 18 19 20 21 22 23 24 25 i pp (a) square wave 2.5s - t=25c v cl (v) 0 1 2 3 4 5 6 7 8 9 10 11 12 012345678910 c(pf) f=1 mhz v osc =30mv rms t j =25c voltage(v) figure 7. relative variation of leakage current versus junction temperature (typical values) figure 8. s21 attenuation measurements 1 10 100 1000 25 50 75 100 125 i r [t j ]/i r [t j =25c] v r =12v t j (c) 100.0k 1.0m 10.0m 100.0m 1.0g -30.00 -24.00 -18.00 -12.00 -6.00 0.00 attenuation db f (hz) < -5.6db (-5.8db@900mhz -10.7db@1.8ghz) attenuation (0.8 ? 4ghz) 505 mhz -3 db point 0.01 db pass band attenuation average performance (50wsystem) < -5.6db (-5.8db@900mhz -10.7db@1.8ghz) attenuation (0.8 ? 4ghz) 505 mhz -3 db point 0.01 db pass band attenuation average performance (50 system)
ordering information scheme ESDA14V2-1BF3 4/9 doc id 15894 rev 1 2 ordering information scheme figure 11. ordering information scheme figure 9. esd response to iec61000-4-2 (+15 kv air discharge) figure 10. esd response to iec61000-4-2 (-15 kv air discharge) 20 v/div 100 ns/div 76 v 20 v/div 100 ns/div -79 v esda 14v2 - 1 b fx esd array breakdown voltage number of lines type package 14v2 = 14.2 volts min. 1 = 1 line b = bidirectional f = flip chip
ESDA14V2-1BF3 package information doc id 15894 rev 1 5/9 3 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 12. package dimensions figure 13. flip chip tape and reel specification 0.36 mm 45 m 0.69 mm 30 m 0.50 mm 30 m 0.40 mm 40 m 0.37 mm 15 m user direction of unreeling all dimensions in mm 4.0 0.1 2.0 0.05 8.0 0.3 2.0 0.1 1.75 0.1 3.5 - 0.05 ? 1.55 0.05 0.43 0.1 0.57 0.05 0.20 0.05 0.75 0.05
pcb recommendations ESDA14V2-1BF3 6/9 doc id 15894 rev 1 4 pcb recommendations 4.1 design for optimum electrical performance and high ly reliable solder joints, stmicroelectronics recommends the pcb design recommendations listed in ta b l e 3 . note: a gold layer finishing on the pcb pad that is too thick (0.2 m maximum) is not recommended (low joint reliability). to optimize the natural self centering effect of csp on the pcb, pcb pad positioning and size have to be properly designed (see figure 14 ) micro vias an alternative to routing on the top surface is to route out on buried layers. to achieve this, the pads are connected to the lower layers us ing micro vias. only ssbu via technology is approved. figure 14. solder mask opening table 3. pcb design recommendations for solder bar pitch 400 m for nsmd pcb non solder mask defined oblong pad: 370 x 180 m ? micro via ssbu allowed ? micro via sbu to be avoided ? micro via sbu filled (under qualification) tr a c k : ? only one track per pad ? maximum track width = 100 m track layout must be symmetrical to the die axis (to homogenize stress and welding attraction during reflow assembly) for smd pcb solder mask defined oblong pad: ? micro via ssbu allowed ? micro via sbu to be avoided ? micro via sbu filled (under qualification) pcb pad finishing cu ? ni (2-6 m) - au (0.2 m max) 370 m 370 m 100 m 450 m 180 m 180 m 255 m non solder mask defined solder mask defined
ESDA14V2-1BF3 pcb recommendations doc id 15894 rev 1 7/9 4.2 assembly for chip scale package mounting on the pcb, stmicroelectronics recommends the use of a solder stencil aperture of 330 x 330 m2 maximum and a typical stencil thickness of 75 or 80 m. chip scale packages are fully compatible with the use of near eutectic 95.5 sn, 4 ag, 0.5 cu solder paste with no-clean flux. st's recommendations for chip scale package board mounting are illustrated on the so ldering reflow profile shown in figure 15 . figure 15. st ecopack? recommended soldering reflow profile for pcb mounting dwell time in the soldering zone (with temperature higher than 220 c) has to be kept as short as possible to prevent component and substrate damages. peak temperature must not exceed 260 c. controlled atmosphere (n2 or n2h2) is recommended during the whole reflow, especially above 150 c. chip scale packages are able to withstand three times the previous recommended reflow profile in order to be compatible with a double reflow when smds are mounted on both sides of the pcb and one additional repair. a maximum of three soldering reflows are allowed for these lead-free packages (with repair step included). the use of a no-clean flux is highly reco mmended to avoid any cleaning operation. to prevent any bump cracks, ultrasonic cleaning methods are not recommended. 0 01234567 time (min) temperature (c) 2c/s recommended 6c/s max 220c 125 c 260c max 255c 180c 90 sec max 10-30 sec 90 to 150 sec 3c/s max 0 01234567 time (min) temperature (c) 2c/s recommended 6c/s max 220c 125 c 260c max 255c 180c 90 sec max 10-30 sec 90 to 150 sec 3c/s max
ordering information ESDA14V2-1BF3 8/9 doc id 15894 rev 1 5 ordering information 6 revision history table 4. ordering information order code marking package weight base qty delivery mode ESDA14V2-1BF3 none flip chip 0.37 mg 15 000 tape and reel 7? table 5. document revision history date revision changes 25-jun-2009 1 initial release.
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